[PATCH] D116397: [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

Quick patch for that, but seems also change the BB layout of 20020529-1...

  diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
  index acd79b4ab742..e8774a033ca3 100644
  --- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
  @@ -251,9 +251,19 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
           continue;
   
         LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
  -      BuildMI(MBB, MI, MI->getDebugLoc(), TII->get(RISCV::COPY),
  -              MI->getOperand(0).getReg())
  -          .add(MI->getOperand(1));
  +      Register DstReg = MI->getOperand(0).getReg();
  +      LLVM_DEBUG(dbgs() << "Replace " << DstReg << " to " << SrcReg << "\n");
  +      // Rewrite all uses.
  +      // const TargetRegisterInfo &TRI = ST.getRegisterInfo();
  +      const TargetRegisterInfo *TRI =
  +          MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
  +      for (MachineBasicBlock &MBB : MF) {
  +        for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
  +          MachineInstr *MI = &*I++;
  +          if (auto MO = MI->findRegisterUseOperand(DstReg))
  +            MO->substVirtReg(SrcReg, 0, *TRI);
  +        }
  +      }
         MI->eraseFromParent();
         ++NumRemovedSExtW;
         MadeChange = true;


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D116397/new/

https://reviews.llvm.org/D116397