[PATCH] D116397: [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 397001.
craig.topper added a comment.

Constrain the reg class before merging the registers. If we can't constrain, don't replace the sext.w.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116397/new/

https://reviews.llvm.org/D116397

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/rv64zbs.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll
  llvm/test/CodeGen/RISCV/split-offsets.ll

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