[PATCH] D116479: [VPlan] Introduce and use ExitCheckAndBranch VPInstruction.

[Ayal Zaks via Phabricator via llvm-commits]

Ayal added a comment.

In D116479#3216412 <https://reviews.llvm.org/D116479#3216412>, @fhahn wrote:

> Move VectorTripCount printing from D113223 <https://reviews.llvm.org/D113223> to this patch.
>
> In D116479#3216397 <https://reviews.llvm.org/D116479#3216397>, @Ayal wrote:
>
>> Combine ExitCheckAndBranch  with CanonicalIVIncrement{NUW} into a single BranchOnCount recipe or two BranchOnCount{NUW} VPInstructions?
>> It is conceptually a single inc-cmp-br idiom, akin to PowerPC's "bdnz" instruction - except instead of decrementing an implicit count register until zero we increment an IV until VectorTripCount.
>
> I'm not sure about the benefits of having the incremenet included in the CheckAndBranch opcode. It would reduce the number of opcodes, but may have the following potential drawbacks:
>
> 1. Once we can model live-ins, we may be able to get rid of the specialized increment opcodes and model it as add with the increment as operand,
> 2. increments for other phi recipes also need to be modeled explicitly, so having an explicit increment for the canonical IV seems more consistent,
> 3. we may want to remove the 'increment' instruction in a VPlan transform in the future, e.g. because we have a canonical vector induction which could be used instead of the scalar one.

Main motivation behind a BranchOnCount recipe is to capture higher semantics and a meaningful idiom in VPlan - clearly modelling the scalar IV which controls a countable loop, rather than minimizing number of opcodes or lowering to ordinary operations. How other IV's should be modelled and optimized is indeed worth addressing, aiming for clarity as well while avoiding premature optimization best left to other passes, e.g., LSR. It should also be possible to optimize BranchOnCount away into other recipes as a VPlan to VPlan transformation, if and when desired.


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