[PATCH] D116421: [RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 396728.
craig.topper added a comment.

Refactor the code to remove the switch and instead use ISD::isSignedIntSetCC and similar helpers.
Don't change the behavior of unsigned(non-equality) comparisons on targets other than RISCV.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116421/new/

https://reviews.llvm.org/D116421

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-convert.ll

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