[PATCH] D116397: [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:61
+// TODO: Allocate a bit in TSFlags for the W instructions?
+// TODO: Add other W instructions.
+static bool isSignExtendingOpW(const MachineInstr &MI) {
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asb wrote:
> Is it just the AMO operations missing?
> 
> Are the missing instructions not listed due to further work being needed, or just lack of test coverage?
The bitmanip instructions that weren’t up for ratification are also missing. Partly because I wasn’t sure if I we’d just have to delete it someday.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116397/new/

https://reviews.llvm.org/D116397