[PATCH] D116397: [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

This is a nice improvement. I'm seeing a few cases where additional moves are generated when this pass is enabled. Presumably this is exposing a problem elsewhere (or just a case where the register allocator is slightly less good) - but I'm wondering if you have looked at this at all?

e.g. 20020529-1.c from the GCC torture suite:

  --- a/output_rv64imafdc_lp64_O3/20020529-1.s
  +++ b/output_rv64imafdc_lp64_O3/20020529-1.s
  @@ -39,9 +39,10 @@ foo:                                    # @foo
          bnez    a0, .LBB0_5
   # %bb.9:                                # %if.end8.us.us
                                           #   in Loop: Header=BB0_8 Depth=1
  -       sext.w  a2, a4
  -       addiw   a4, a4, 1
  -       bne     a2, a1, .LBB0_8
  +       addiw   a2, a4, 1
  +       mv      a3, a4
  +       mv      a4, a2
  +       bne     a3, a1, .LBB0_8
   .LBB0_10:                               # %if.then
          lui     a0, %hi(f1.beenhere)
          li      a1, 2



================
Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:61
+// TODO: Allocate a bit in TSFlags for the W instructions?
+// TODO: Add other W instructions.
+static bool isSignExtendingOpW(const MachineInstr &MI) {
----------------
Is it just the AMO operations missing?

Are the missing instructions not listed due to further work being needed, or just lack of test coverage?


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:202
+
+  addPass(createRISCVSExtWRemovalPass());
+}
----------------
Only add the pass if targeting RV64?


Repository:
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  https://reviews.llvm.org/D116397/new/

https://reviews.llvm.org/D116397