[llvm] 33fc675 - [Hexagon] Handle floating point vector loads/stores
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 29 05:53:04 PST 2021
Author: Krzysztof Parzyszek
Date: 2021-12-29T05:52:39-08:00
New Revision: 33fc675e1670939cb3b037bf669ca6d1efa3eb1f
URL: https://github.com/llvm/llvm-project/commit/33fc675e1670939cb3b037bf669ca6d1efa3eb1f
DIFF: https://github.com/llvm/llvm-project/commit/33fc675e1670939cb3b037bf669ca6d1efa3eb1f.diff
LOG: [Hexagon] Handle floating point vector loads/stores
Added:
llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
Modified:
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index 15fa659d26aba..21e703fd5a3c5 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -165,12 +165,19 @@ let Predicates = [UseHVX] in {
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
-
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;
defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;
}
+let Predicates = [UseHVXV68] in {
+ defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecF16, IsVecOff>;
+ defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecF32, IsVecOff>;
+ defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecF16, IsVecOff>;
+ defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecF32, IsVecOff>;
+ defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecF16, IsVecOff>;
+ defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecF32, IsVecOff>;
+}
// HVX stores
@@ -214,6 +221,15 @@ let Predicates = [UseHVX] in {
defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI32, IsVecOff>;
}
+let Predicates = [UseHVXV68] in {
+ defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVF16, IsVecOff>;
+ defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVF32, IsVecOff>;
+ defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVF16, IsVecOff>;
+ defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVF32, IsVecOff>;
+ defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVF16, IsVecOff>;
+ defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVF32, IsVecOff>;
+}
+
// Bitcasts between same-size vector types are no-ops, except for the
// actual type change.
let Predicates = [UseHVX] in {
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
new file mode 100644
index 0000000000000..3b01f971bad2f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(<128 x i8>* %a0, <128 x i8>* %a1) #0 {
+; CHECK-LABEL: f0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0.cur = vmem(r0+#1)
+; CHECK-NEXT: vmem(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <128 x i8>, <128 x i8>* %a0, i32 1
+ %v1 = load <128 x i8>, <128 x i8>* %v0, align 128
+ %v2 = getelementptr <128 x i8>, <128 x i8>* %a1, i32 2
+ store <128 x i8> %v1, <128 x i8>* %v2, align 128
+ ret void
+}
+
+define void @f1(<64 x i16>* %a0, <64 x i16>* %a1) #0 {
+; CHECK-LABEL: f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0.cur = vmem(r0+#1)
+; CHECK-NEXT: vmem(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <64 x i16>, <64 x i16>* %a0, i32 1
+ %v1 = load <64 x i16>, <64 x i16>* %v0, align 128
+ %v2 = getelementptr <64 x i16>, <64 x i16>* %a1, i32 2
+ store <64 x i16> %v1, <64 x i16>* %v2, align 128
+ ret void
+}
+
+define void @f2(<32 x i32>* %a0, <32 x i32>* %a1) #0 {
+; CHECK-LABEL: f2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0.cur = vmem(r0+#1)
+; CHECK-NEXT: vmem(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <32 x i32>, <32 x i32>* %a0, i32 1
+ %v1 = load <32 x i32>, <32 x i32>* %v0, align 128
+ %v2 = getelementptr <32 x i32>, <32 x i32>* %a1, i32 2
+ store <32 x i32> %v1, <32 x i32>* %v2, align 128
+ ret void
+}
+
+define void @f3(<64 x half>* %a0, <64 x half>* %a1) #0 {
+; CHECK-LABEL: f3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0.cur = vmem(r0+#1)
+; CHECK-NEXT: vmem(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <64 x half>, <64 x half>* %a0, i32 1
+ %v1 = load <64 x half>, <64 x half>* %v0, align 128
+ %v2 = getelementptr <64 x half>, <64 x half>* %a1, i32 2
+ store <64 x half> %v1, <64 x half>* %v2, align 128
+ ret void
+}
+
+define void @f4(<32 x float>* %a0, <32 x float>* %a1) #0 {
+; CHECK-LABEL: f4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0.cur = vmem(r0+#1)
+; CHECK-NEXT: vmem(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <32 x float>, <32 x float>* %a0, i32 1
+ %v1 = load <32 x float>, <32 x float>* %v0, align 128
+ %v2 = getelementptr <32 x float>, <32 x float>* %a1, i32 2
+ store <32 x float> %v1, <32 x float>* %v2, align 128
+ ret void
+}
+
+define void @f5(<128 x i8>* %a0, <128 x i8>* %a1) #0 {
+; CHECK-LABEL: f5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vmemu(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: vmemu(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <128 x i8>, <128 x i8>* %a0, i32 1
+ %v1 = load <128 x i8>, <128 x i8>* %v0, align 1
+ %v2 = getelementptr <128 x i8>, <128 x i8>* %a1, i32 2
+ store <128 x i8> %v1, <128 x i8>* %v2, align 1
+ ret void
+}
+
+define void @f6(<64 x i16>* %a0, <64 x i16>* %a1) #0 {
+; CHECK-LABEL: f6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vmemu(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: vmemu(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <64 x i16>, <64 x i16>* %a0, i32 1
+ %v1 = load <64 x i16>, <64 x i16>* %v0, align 1
+ %v2 = getelementptr <64 x i16>, <64 x i16>* %a1, i32 2
+ store <64 x i16> %v1, <64 x i16>* %v2, align 1
+ ret void
+}
+
+define void @f7(<32 x i32>* %a0, <32 x i32>* %a1) #0 {
+; CHECK-LABEL: f7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vmemu(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: vmemu(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <32 x i32>, <32 x i32>* %a0, i32 1
+ %v1 = load <32 x i32>, <32 x i32>* %v0, align 1
+ %v2 = getelementptr <32 x i32>, <32 x i32>* %a1, i32 2
+ store <32 x i32> %v1, <32 x i32>* %v2, align 1
+ ret void
+}
+
+define void @f8(<64 x half>* %a0, <64 x half>* %a1) #0 {
+; CHECK-LABEL: f8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vmemu(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: vmemu(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <64 x half>, <64 x half>* %a0, i32 1
+ %v1 = load <64 x half>, <64 x half>* %v0, align 1
+ %v2 = getelementptr <64 x half>, <64 x half>* %a1, i32 2
+ store <64 x half> %v1, <64 x half>* %v2, align 1
+ ret void
+}
+
+define void @f9(<32 x float>* %a0, <32 x float>* %a1) #0 {
+; CHECK-LABEL: f9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: v0 = vmemu(r0+#1)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: vmemu(r1+#2) = v0
+; CHECK-NEXT: }
+ %v0 = getelementptr <32 x float>, <32 x float>* %a0, i32 1
+ %v1 = load <32 x float>, <32 x float>* %v0, align 1
+ %v2 = getelementptr <32 x float>, <32 x float>* %a1, i32 2
+ store <32 x float> %v1, <32 x float>* %v2, align 1
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }
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