[PATCH] D116042: [AMDGPU][InstCombine] Remove zero LOD bias

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6249
 
-  // Optimize _L to _LZ when _L is zero
-  if (LZMappingInfo) {
----------------
I would split the codegen change into a separate patch


================
Comment at: llvm/test/CodeGen/AMDGPU/image_ls_mipmap_zero.ll:132
-attributes #1 = { nounwind readonly }
-
----------------
I don't know about deleting codegen tests for this, these still show the behavior in this scenario


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116042/new/

https://reviews.llvm.org/D116042