[PATCH] D114640: [PowerPC] Handle Vector Sum Reduction

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10757
+  case MVT::v16i32: {
+    if (VecInput.getOpcode() != ISD::SIGN_EXTEND &&
+        VecInput.getOpcode() != ISD::ZERO_EXTEND)
----------------
amyk wrote:
> It looks like this portion:
> ```
>     if (VecInput.getOpcode() != ISD::SIGN_EXTEND &&
>         VecInput.getOpcode() != ISD::ZERO_EXTEND)
>       return SDValue();
> 
>     // Check that we are extending from v16i8 to v16i32.
>     if (VecInput.getOperand(0).getSimpleValueType() != MVT::v16i8)
>       return SDValue();
> ```
> is common in both cases. Does it make sense to pull this part out of the case statements so we don't duplicate it?
There is actually more common code between the two case statements. I think I'm going to merge to two cases but I don't want to pull the if statements out of the switch. The way that I look at this is that anything that is outside the switch should apply to all of the possible types in the switch. Since I cannot guarantee that for those two early exists I will just leave them in the switch.


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  https://reviews.llvm.org/D114640/new/

https://reviews.llvm.org/D114640