[PATCH] D114640: [PowerPC] Handle Vector Sum Reduction

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp:93
+  // Only expand types that are fed by zero extends or sign extends.
+  if (OperandInstr->getOpcode() != Instruction::SExt &&
+      OperandInstr->getOpcode() != Instruction::ZExt)
----------------
amyk wrote:
> I think it would be good to save the opcode first, and then use it in this condition.
Sounds good. I will do that!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114640/new/

https://reviews.llvm.org/D114640