[PATCH] D115863: [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

[David Sherwood via Phabricator via llvm-commits]

david-arm updated this revision to Diff 395096.
david-arm added a comment.

- Removed check for minimum number of elements by ensuring that the intrinsic will never contain indices that are out-of-bounds (see D115933 <https://reviews.llvm.org/D115933>).
- Added more indices by seeing if the index is a supported pattern for the ptrue instruction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115863/new/

https://reviews.llvm.org/D115863

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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