[PATCH] D115863: [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE

Thu Dec 16 05:29:06 PST 2021

david-arm added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7798
+  if (Ty.isScalableVector() && IdxVal >= -8 && IdxVal <= -1 &&
+      -IdxVal <= Ty.getVectorMinNumElements()) {
+    SDLoc DL(Op);
----------------
sdesmalen wrote:
> david-arm wrote:
> > sdesmalen wrote:
> > > I don't think this check is necessary?
> > Unforunately, it is necessary for correctness because the ptrue behaviour changes completely when you specify a fixed pattern that exceeds the number of elements. For example, if we do something like this:
> > 
> >   ptrue p0.d, vl4
> > 
> > and your vector length=128 bits, then ptrue actually returns an all-false predicate! So the maximum we can do safely without knowing vscale is:
> > 
> >   ptrue p0.d, vl2
> If that happens it means that the original IR was incorrect, because it should never have generated a splice with offset `-4` for a ``vscale x 2 x eltty>` if vscale can be lower than 2. This can be verified in the IR Verifier with an extra check on `vscale_range` , but it shouldn't be part of the check here.
OK, in that case maybe I can just change this to an assert and I will add code to the verifier as part of this patch if it's not already there.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115863/new/

https://reviews.llvm.org/D115863