[PATCH] D114361: [MachineCSE] Add an option to enable global CSE

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead updated this revision to Diff 394746.
pcwang-thead added a comment.

- Rebase.
- Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114361/new/

https://reviews.llvm.org/D114361

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MachineCSE.cpp


Index: llvm/lib/CodeGen/MachineCSE.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCSE.cpp
+++ llvm/lib/CodeGen/MachineCSE.cpp
@@ -51,6 +51,10 @@
 
 #define DEBUG_TYPE "machine-cse"
 
+static cl::opt<bool> EnableAggressiveMachineCSE(
+    "enable-aggressive-machine-cse", cl::Hidden, cl::init(false),
+    cl::desc("Enable aggressive machine CSE on the whole function."));
+
 STATISTIC(NumCoalesces, "Number of copies coalesced");
 STATISTIC(NumCSEs,      "Number of common subexpression eliminated");
 STATISTIC(NumPREs,      "Number of partial redundant expression"
@@ -70,6 +74,7 @@
     MachineDominatorTree *DT;
     MachineRegisterInfo *MRI;
     MachineBlockFrequencyInfo *MBFI;
+    bool AggressiveMachineCSE;
 
   public:
     static char ID; // Pass identification
@@ -454,7 +459,7 @@
   // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
   // an immediate predecessor. We don't want to increase register pressure and
   // end up causing other computation to be spilled.
-  if (TII->isAsCheapAsAMove(*MI)) {
+  if (TII->isAsCheapAsAMove(*MI) && !AggressiveMachineCSE) {
     MachineBasicBlock *BB = MI->getParent();
     if (CSBB != BB && !CSBB->isSuccessor(BB))
       return false;
@@ -913,6 +918,9 @@
   DT = &getAnalysis<MachineDominatorTree>();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   LookAheadLimit = TII->getMachineCSELookAheadLimit();
+  AggressiveMachineCSE =
+      EnableAggressiveMachineCSE || TII->enableAggressiveMachineCSE(MF);
+
   bool ChangedPRE, ChangedCSE;
   ChangedPRE = PerformSimplePRE(DT);
   ChangedCSE = PerformCSE(DT->getRootNode());
Index: llvm/include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -375,6 +375,13 @@
     return MI.isAsCheapAsAMove();
   }
 
+  /// Return true if we want to do aggressive MachineCSE.
+  ///
+  /// Aggressive MachineCSE can be enabled when optimizing for size.
+  virtual bool enableAggressiveMachineCSE(const MachineFunction &MF) const {
+    return false;
+  }
+
   /// Return true if the instruction should be sunk by MachineSink.
   ///
   /// MachineSink determines on its own whether the instruction is safe to sink;


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