[llvm] d3c2ad1 - [RISCV] Fix whole vector register move instruction's vector register constraint.

[via llvm-commits]

Author: jacquesguan
Date: 2021-12-16T10:58:55+08:00
New Revision: d3c2ad154ec8bcea0a4ac602bc17e5d9d4cdd27f

URL: https://github.com/llvm/llvm-project/commit/d3c2ad154ec8bcea0a4ac602bc17e5d9d4cdd27f
DIFF: https://github.com/llvm/llvm-project/commit/d3c2ad154ec8bcea0a4ac602bc17e5d9d4cdd27f.diff

LOG: [RISCV] Fix whole vector register move instruction's vector register constraint.

According to the v-spec, the source and destination VR of vmv<nr>r.v should be aligned for the VR group size.

Differential Revision: https://reviews.llvm.org/D115720

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/test/MC/RISCV/rvv/invalid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 3d5f9bc54731e..a906e88c22103 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1416,13 +1416,20 @@ defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
     RVVConstraint = NoConstraint in {
-foreach n = [1, 2, 4, 8] in {
-  def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs VR:$vd),
-                           (ins VR:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
-                   VMVRSched<n> {
+def VMV1R_V  : RVInstV<0b100111, 0, OPIVI, (outs VR:$vd), (ins VR:$vs2),
+                       "vmv1r.v", "$vd, $vs2">, VMVRSched<1> {
   let Uses = [];
   let vm = 1;
 }
+// A future extension may relax the vector register alignment restrictions.
+foreach n = [2, 4, 8] in {
+  defvar vrc = !cast<VReg>("VRM"#n);
+  def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
+                           (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
+                   VMVRSched<n> {
+    let Uses = [];
+    let vm = 1;
+  }
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]

diff  --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 501cbe2854e95..55eba3afb00f2 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -661,6 +661,72 @@ vs8r.v v6, (a0)
 vs8r.v v7, (a0)
 # CHECK-ERROR: invalid operand for instruction
 
+vmv2r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv2r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v2, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v3, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v2
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v3
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v2, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v3, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v4, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v5, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v6, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v7, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v2
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v3
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v4
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v5
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v6
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v7
+# CHECK-ERROR: invalid operand for instruction
+
 vmsge.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction