[PATCH] D115810: [RISCV] Don't allow vector types to be used with inline asm 'r' constraint
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 15 11:11:44 PST 2021
jrtc27 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9593
case 'f':
if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
return std::make_pair(0U, &RISCV::FPR16RegClass);
----------------
craig.topper wrote:
> While I'm here. This should be Zfhmin right?
Yeah
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D115810/new/
https://reviews.llvm.org/D115810
More information about the llvm-commits
mailing list