[PATCH] D115810: [RISCV] Don't allow vector types to be used with inline asm 'r' constraint

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9593
     case 'f':
       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);
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While I'm here. This should be Zfhmin right?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115810/new/

https://reviews.llvm.org/D115810