[PATCH] D115810: [RISCV] Don't allow vector types to be used with inline asm 'r' constraint

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9589
     case 'r':
-      return std::make_pair(0U, &RISCV::GPRRegClass);
+      if (!VT.isVector())
+        return std::make_pair(0U, &RISCV::GPRRegClass);
----------------
```
if (VT.isVector())
  break;
```
is a bit more extensible in that line lengths don't get stupidly long as the list grows; we exclude our own register class from r downstream like that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115810/new/

https://reviews.llvm.org/D115810