[PATCH] D115810: [RISCV] Don't allow vector types to be used with inline asm 'r' constraint

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The 'r' constraint uses the GPR class. There is generic support
for bitcasting and extending/truncating non-integer VTs to the
required integer VT. This doesn't work for scalable vectors and
instead crashes.

To prevent this, explicitly reject vectors. Fixed vectors might
work without crashing, but it doesn't seem worthwhile to allow.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115810

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/inline-asm-invalid.ll


Index: llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
+++ llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
@@ -30,3 +30,15 @@
   tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
   ret void
 }
+
+define void @constraint_r_fixed_vec() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'r'
+  tail call void asm "add a0, a0, $0", "r"(<4 x i32> zeroinitializer)
+  ret void
+}
+
+define void @constraint_r_scalable_vec() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'r'
+  tail call void asm "add a0, a0, $0", "r"(<vscale x 4 x i32> zeroinitializer)
+  ret void
+}
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9586,7 +9586,9 @@
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
-      return std::make_pair(0U, &RISCV::GPRRegClass);
+      if (!VT.isVector())
+        return std::make_pair(0U, &RISCV::GPRRegClass);
+      break;
     case 'f':
       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);
@@ -9598,17 +9600,15 @@
     default:
       break;
     }
-  } else {
-    if (Constraint == "vr") {
-      for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
-                             &RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) {
-        if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
-          return std::make_pair(0U, RC);
-      }
-    } else if (Constraint == "vm") {
-      if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
-        return std::make_pair(0U, &RISCV::VMV0RegClass);
+  } else if (Constraint == "vr") {
+    for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
+                           &RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) {
+      if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
+        return std::make_pair(0U, RC);
     }
+  } else if (Constraint == "vm") {
+    if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
+      return std::make_pair(0U, &RISCV::VMV0RegClass);
   }
 
   // Clang will correctly decode the usage of register name aliases into their


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