[PATCH] D115739: [SVE][DAGCombiner] Enable ISD::ABDS and ISD::ABDU for SVE.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9351
+  if (TLI.isOperationLegalOrCustom(ABDOpcode, VT))
+    return DAG.getNode(ABDOpcode, SDLoc(N), VT, Op0, Op1);
+
----------------
If I'm understanding correctly, this is just saying that if you know some number of leading sign bits of the operands, abs(a-b) is equivalent to abds(a,b) (and the equivalent for unsigned).

This would be more clear if you explicitly checked for leading zero/sign bits, instead of implying them from a SIGN_EXTEND/ZERO_EXTEND opcode.

I'd like to see non-SVE testcases for this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115739/new/

https://reviews.llvm.org/D115739