[PATCH] D115739: [SVE][DAGCombiner] Enable ISD::ABDS and ISD::ABDU for SVE.

[Paul Walker via Phabricator via llvm-commits]

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Add the typical custom lowering and isel patterns to enable ABD
for scalable vectors.

The existing ABD combine doesn't quite work because for SVE only
a single scalable vector per scalar integer type it legal. (i.e.
for i32, <vscale x 4 x i32> is the only legal scalable vector type)

To account for this I've extended the combine for the case when the
extension of the input operands cannot be folded into the ABD. The
accompanying tests use legal and twice-the-size of legal types to
exercise both combines.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115739

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-abd.ll

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