[llvm] 16de2c0 - [AMDGPU] SIShrinkInstructions: sink code to where it's used. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-12-13T14:46:40Z
New Revision: 16de2c09dd5ee388a9d7aee2e4c2402d17f1ce1c

URL: https://github.com/llvm/llvm-project/commit/16de2c09dd5ee388a9d7aee2e4c2402d17f1ce1c
DIFF: https://github.com/llvm/llvm-project/commit/16de2c09dd5ee388a9d7aee2e4c2402d17f1ce1c.diff

LOG: [AMDGPU] SIShrinkInstructions: sink code to where it's used. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 774e2b3d218d..c8f1daf26de9 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -771,10 +771,6 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
       const MachineOperand *SDst = TII->getNamedOperand(MI,
                                                         AMDGPU::OpName::sdst);
 
-      // Check the carry-in operand for v_addc_u32_e64.
-      const MachineOperand *Src2 = TII->getNamedOperand(MI,
-                                                        AMDGPU::OpName::src2);
-
       if (SDst) {
         bool Next = false;
 
@@ -786,6 +782,8 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
 
         // All of the instructions with carry outs also have an SGPR input in
         // src2.
+        const MachineOperand *Src2 = TII->getNamedOperand(MI,
+                                                          AMDGPU::OpName::src2);
         if (Src2 && Src2->getReg() != VCCReg) {
           if (Src2->getReg().isVirtual())
             MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg);