[PATCH] D115217: [NFC][MachineFunction] Rename APIs to conform to coding style

[Mircea Trofin via Phabricator via llvm-commits]

mtrofin created this revision.
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Function names should start with lowercase, so renamed accordingly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115217

Files:
  llvm/include/llvm/CodeGen/MachineFunction.h
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/CodeGen/MachineInstrBuilder.h
  llvm/lib/CodeGen/BasicBlockSections.cpp
  llvm/lib/CodeGen/BranchFolding.cpp
  llvm/lib/CodeGen/BranchRelaxation.cpp
  llvm/lib/CodeGen/CodeGenCommonISel.cpp
  llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/GlobalISel/Localizer.cpp
  llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
  llvm/lib/CodeGen/IfConversion.cpp
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MIRSampleProfile.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/MachineFunctionSplitter.cpp
  llvm/lib/CodeGen/MachineLoopUtils.cpp
  llvm/lib/CodeGen/MachineOutliner.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/ModuloSchedule.cpp
  llvm/lib/CodeGen/PHIElimination.cpp
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SwitchLoweringUtils.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/CodeGen/UnreachableBlockElim.cpp
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
  llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBlockPlacement.cpp
  llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/lib/Target/MSP430/MSP430BranchSelector.cpp
  llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
  llvm/lib/Target/Mips/Mips16ISelLowering.cpp
  llvm/lib/Target/Mips/MipsBranchExpansion.cpp
  llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
  llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
  llvm/lib/Target/Mips/MipsExpandPseudo.cpp
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsSEISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
  llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
  llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
  llvm/lib/Target/PowerPC/PPCExpandISEL.cpp
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
  llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
  llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/VE/VEInstrInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/lib/Target/X86/X86CmovConversion.cpp
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  llvm/lib/Target/X86/X86FloatingPoint.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86IndirectThunks.cpp
  llvm/lib/Target/X86/X86InsertPrefetch.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  llvm/lib/Target/XCore/XCoreISelLowering.cpp
  llvm/tools/llvm-exegesis/lib/Assembler.cpp
  llvm/tools/llvm-reduce/ReducerWorkItem.cpp
  llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
  llvm/unittests/CodeGen/InstrRefLDVTest.cpp
  llvm/unittests/CodeGen/LexicalScopesTest.cpp
  llvm/unittests/CodeGen/MachineInstrTest.cpp
  llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp

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