[PATCH] D115547: [X86] Adjust some IceLake integer shuffle schedule classes (PR48110)

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added a comment.

Thanks @RKSimon for working on it. Do we have an easy way to check if the change covers all shuffle instructions and the value is matched with Agner + uops.info?



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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:391
 defm : ICXWriteResPair<WritePMULLDZ,  [ICXPort05], 10, [2], 2, 7>;
-defm : ICXWriteResPair<WriteShuffle,  [ICXPort5], 1, [1], 1, 5>; // Vector shuffles.
-defm : ICXWriteResPair<WriteShuffleX, [ICXPort5], 1, [1], 1, 6>;
-defm : ICXWriteResPair<WriteShuffleY, [ICXPort5], 1, [1], 1, 7>;
-defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>;
-defm : ICXWriteResPair<WriteVarShuffle,  [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
-defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort5], 1, [1], 1, 6>;
-defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort5], 1, [1], 1, 7>;
-defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>;
+defm : ICXWriteResPair<WriteShuffle,  [ICXPort5],  1, [1], 1, 5>; // Vector shuffles.
+defm : ICXWriteResPair<WriteShuffleX, [ICXPort15], 1, [1], 1, 6>;
----------------
What's `WriteShuffle` used for? I saw some `*Z128` use it as well. Why does it only work on port5?


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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:668
+                                            "VPBROADCAST(D|Q)rr",
+                                            "(V)?PALIGNR(Y|Z128|Z256)?rri",
+                                            "(V?)PACK(U|S)S(DW|WB)(Y|Z128|Z256)?rr")>;
----------------
Just for curious, what's the difference between `(V)?` and `(V?)`


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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:668
+                                            "VPBROADCAST(D|Q)rr",
+                                            "(V)?PALIGNR(Y|Z128|Z256)?rri",
+                                            "(V?)PACK(U|S)S(DW|WB)(Y|Z128|Z256)?rr")>;
----------------
pengfei wrote:
> Just for curious, what's the difference between `(V)?` and `(V?)`
`Y|Z|Z128|Z256`?


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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:669
+                                            "(V)?PALIGNR(Y|Z128|Z256)?rri",
+                                            "(V?)PACK(U|S)S(DW|WB)(Y|Z128|Z256)?rr")>;
 
----------------
`Y|Z|Z128|Z256`?


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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:1544
+                                              "VPBROADCASTW(Z|Z256)rm(b?)",
+                                              "(V)?PALIGNR(Y|Z256)rmi",
+                                              "(V?)PACK(U|S)S(DW|WB)(Y|Z256)rm")>;
----------------
`Y|Z|Z256`


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Comment at: llvm/lib/Target/X86/X86SchedIceLake.td:1545
+                                              "(V)?PALIGNR(Y|Z256)rmi",
+                                              "(V?)PACK(U|S)S(DW|WB)(Y|Z256)rm")>;
 def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm,
----------------
ditto?


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Comment at: llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s:1568
 # CHECK-NEXT:  2      7     0.50    *                   vpslld	(%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     1.00                        vpslldq	$1, %xmm1, %xmm2
+# CHECK-NEXT:  1      1     0.50                        vpslldq	$1, %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpsllq	$1, %xmm0, %xmm2
----------------
Why is it affected?


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Comment at: llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s:1584
 # CHECK-NEXT:  2      7     0.50    *                   vpsrld	(%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     1.00                        vpsrldq	$1, %xmm1, %xmm2
+# CHECK-NEXT:  1      1     0.50                        vpsrldq	$1, %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpsrlq	$1, %xmm0, %xmm2
----------------
ditto.


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  https://reviews.llvm.org/D115547/new/

https://reviews.llvm.org/D115547