[PATCH] D115259: [AArch64][SVE] Lower vector.insert to predicated SEL

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau marked 2 inline comments as done.
MattDevereau added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll:82
 ; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
-; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    str q1, [sp]
-; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
-; CHECK-NEXT:    addvl sp, sp, #1
-; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    sel z0.h, p0, z0.h, z1.h
 ; CHECK-NEXT:    ret
----------------
paulwalker-arm wrote:
> Is this not backwards? `SEL` says "Read active elements from the first source vector and inactive elements from the second source vector" so the subvector should be the first source?
Yes, it was backwards. Swapping the operands has made it generate a MOV alias of SEL instead which seems more appropriate.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115259/new/

https://reviews.llvm.org/D115259