[PATCH] D115259: [AArch64][SVE] Lower vector.insert to predicated SEL

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 392721.
MattDevereau added a comment.

combined similar if statement logic


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115259/new/

https://reviews.llvm.org/D115259

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/split-vector-insert.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll

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