[llvm] 698584f - [IR] Remove unbounded as possible value for vscale_range minimum
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 7 01:52:55 PST 2021
Author: Cullen Rhodes
Date: 2021-12-07T09:52:21Z
New Revision: 698584f89b8f8bd7f6c2d2cd61efb5548857da2a
URL: https://github.com/llvm/llvm-project/commit/698584f89b8f8bd7f6c2d2cd61efb5548857da2a
DIFF: https://github.com/llvm/llvm-project/commit/698584f89b8f8bd7f6c2d2cd61efb5548857da2a.diff
LOG: [IR] Remove unbounded as possible value for vscale_range minimum
The default for min is changed to 1. The behaviour of -mvscale-{min,max}
in Clang is also changed such that 16 is the max vscale when targeting
SVE and no max is specified.
Reviewed By: sdesmalen, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D113294
Added:
clang/test/Frontend/aarch64-vscale-min.c
Modified:
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
llvm/docs/LangRef.rst
llvm/include/llvm/IR/Attributes.h
llvm/lib/IR/Attributes.cpp
llvm/lib/IR/Verifier.cpp
llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
llvm/test/Bitcode/attributes.ll
llvm/test/Transforms/InstCombine/icmp-vscale.ll
llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
llvm/test/Transforms/InstCombine/vscale_trunc.ll
llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
llvm/test/Verifier/vscale_range.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 2f50918b527be..3638d07cc3b35 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -608,6 +608,8 @@ def err_cc1_round_trip_ok_then_fail : Error<
"generated arguments parse failed in round-trip">;
def err_cc1_round_trip_mismatch : Error<
"generated arguments do not match in round-trip">;
+def err_cc1_unbounded_vscale_min : Error<
+ "minimum vscale must be an unsigned integer greater than 0">;
def err_drv_ssp_missing_offset_argument : Error<
"'%0' is used without '-mstack-protector-guard-offset', and there is no default">;
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 9d5f021102a5e..e9c3ece3d1634 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3357,8 +3357,7 @@ def msve_vector_bits_EQ : Joined<["-"], "msve-vector-bits=">, Group<m_aarch64_Fe
def mvscale_min_EQ : Joined<["-"], "mvscale-min=">,
Group<m_aarch64_Features_Group>, Flags<[NoXarchOption,CC1Option]>,
- HelpText<"Specify the vscale minimum. Defaults to the"
- " vector length agnostic value of \"0\". (AArch64 only)">,
+ HelpText<"Specify the vscale minimum. Defaults to \"1\". (AArch64 only)">,
MarshallingInfoInt<LangOpts<"VScaleMin">>;
def mvscale_max_EQ : Joined<["-"], "mvscale-max=">,
Group<m_aarch64_Features_Group>, Flags<[NoXarchOption,CC1Option]>,
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 4d403ae1809d4..0212889811486 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -474,10 +474,12 @@ ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
Optional<std::pair<unsigned, unsigned>>
AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
- return std::pair<unsigned, unsigned>(LangOpts.VScaleMin,
- LangOpts.VScaleMax);
+ return std::pair<unsigned, unsigned>(
+ LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
+
if (hasFeature("sve"))
- return std::pair<unsigned, unsigned>(0, 16);
+ return std::pair<unsigned, unsigned>(1, 16);
+
return None;
}
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index c104a6f40e20f..f760eb284e75f 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -4123,6 +4123,13 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
{std::string(Split.first), std::string(Split.second)});
}
+ // Error if -mvscale-min is unbounded.
+ if (Arg *A = Args.getLastArg(options::OPT_mvscale_min_EQ)) {
+ unsigned VScaleMin;
+ if (StringRef(A->getValue()).getAsInteger(10, VScaleMin) || VScaleMin == 0)
+ Diags.Report(diag::err_cc1_unbounded_vscale_min);
+ }
+
return Diags.getNumErrors() == NumErrorsBefore;
}
diff --git a/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c b/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
index 210251d765f49..5f17800cb3470 100644
--- a/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
+++ b/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
@@ -10,12 +10,13 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4 --check-prefix=CHECK-NOMAX
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 --check-prefix=CHECK-NOMAX
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 --check-prefix=CHECK-NOMAX
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -mvscale-min=0 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=0 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-UNBOUNDED
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-UNBOUNDED
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
// CHECK-LABEL: @func() #0
// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
// CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
-// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(0,16) {{.*}} }
+// CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
+// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(1,16) {{.*}} }
void func() {}
diff --git a/clang/test/Frontend/aarch64-vscale-min.c b/clang/test/Frontend/aarch64-vscale-min.c
new file mode 100644
index 0000000000000..4cf9badc78b74
--- /dev/null
+++ b/clang/test/Frontend/aarch64-vscale-min.c
@@ -0,0 +1,10 @@
+// -----------------------------------------------------------------------------
+// Tests for the -mvscale-min flag
+// -----------------------------------------------------------------------------
+
+// Error out if value is unbounded.
+// -----------------------------------------------------------------------------
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN: -mvscale-min=0 2>&1 | FileCheck %s
+
+// CHECK: error: minimum vscale must be an unsigned integer greater than 0
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 92aa8f7f1efda..af2b0aee44e92 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -2134,9 +2134,10 @@ example:
duplicate definitions are linked together with
diff ering values.
``vscale_range(<min>[, <max>])``
This attribute indicates the minimum and maximum vscale value for the given
- function. A value of 0 means unbounded. If the optional max value is omitted
- then max is set to the value of min. If the attribute is not present, no
- assumptions are made about the range of vscale.
+ function. The min must be greater than 0. A maximum value of 0 means
+ unbounded. If the optional max value is omitted then max is set to the
+ value of min. If the attribute is not present, no assumptions are made
+ about the range of vscale.
Call Site Attributes
----------------------
diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h
index 282be640d8be7..906aba0264491 100644
--- a/llvm/include/llvm/IR/Attributes.h
+++ b/llvm/include/llvm/IR/Attributes.h
@@ -216,7 +216,7 @@ class Attribute {
/// if not known).
std::pair<unsigned, Optional<unsigned>> getAllocSizeArgs() const;
- /// Returns the argument numbers for the vscale_range attribute (or pair(0, 0)
+ /// Returns the argument numbers for the vscale_range attribute (or pair(1, 0)
/// if not known).
std::pair<unsigned, unsigned> getVScaleRangeArgs() const;
@@ -1054,7 +1054,7 @@ class AttrBuilder {
std::pair<unsigned, Optional<unsigned>> getAllocSizeArgs() const;
/// Retrieve the vscale_range args, if the vscale_range attribute exists. If
- /// it doesn't exist, pair(0, 0) is returned.
+ /// it doesn't exist, pair(1, 0) is returned.
std::pair<unsigned, unsigned> getVScaleRangeArgs() const;
/// Add integer attribute with raw value (packed/encoded if necessary).
diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp
index f81a446d6e46d..d0bc53bc8e4f8 100644
--- a/llvm/lib/IR/Attributes.cpp
+++ b/llvm/lib/IR/Attributes.cpp
@@ -719,7 +719,7 @@ std::pair<unsigned, Optional<unsigned>> AttributeSet::getAllocSizeArgs() const {
std::pair<unsigned, unsigned> AttributeSet::getVScaleRangeArgs() const {
return SetNode ? SetNode->getVScaleRangeArgs()
- : std::pair<unsigned, unsigned>(0, 0);
+ : std::pair<unsigned, unsigned>(1, 0);
}
std::string AttributeSet::getAsString(bool InAttrGrp) const {
@@ -900,7 +900,7 @@ AttributeSetNode::getAllocSizeArgs() const {
std::pair<unsigned, unsigned> AttributeSetNode::getVScaleRangeArgs() const {
if (auto A = findEnumAttribute(Attribute::VScaleRange))
return A->getVScaleRangeArgs();
- return std::make_pair(0, 0);
+ return std::make_pair(1, 0);
}
std::string AttributeSetNode::getAsString(bool InAttrGrp) const {
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 154b59835b01f..1290f5e08d250 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -2058,6 +2058,9 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs,
std::pair<unsigned, unsigned> Args =
Attrs.getFnAttrs().getVScaleRangeArgs();
+ if (Args.first == 0)
+ CheckFailed("'vscale_range' minimum must be greater than 0", V);
+
if (Args.first > Args.second && Args.second != 0)
CheckFailed("'vscale_range' minimum cannot be greater than maximum", V);
}
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll b/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
index b932a980c9aa9..61cd1750d6939 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
@@ -104,8 +104,8 @@ define void @masked_gathers_no_vscale_range() #2 {
ret void
}
-attributes #0 = { "target-features"="+sve" vscale_range(0, 8) }
-attributes #1 = { "target-features"="+sve" vscale_range(0, 16) "tune-cpu"="generic" }
+attributes #0 = { "target-features"="+sve" vscale_range(1, 8) }
+attributes #1 = { "target-features"="+sve" vscale_range(1, 16) "tune-cpu"="generic" }
attributes #2 = { "target-features"="+sve" }
declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32(<vscale x 4 x i32*>, i32, <vscale x 4 x i1>, <vscale x 4 x i32>)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll b/llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
index a3454084e5f5e..9e2948cc46893 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
@@ -104,8 +104,8 @@ define void @masked_scatters_no_vscale_range() #2 {
ret void
}
-attributes #0 = { "target-features"="+sve" vscale_range(0, 8) }
-attributes #1 = { "target-features"="+sve" vscale_range(0, 16) "tune-cpu"="generic" }
+attributes #0 = { "target-features"="+sve" vscale_range(1, 8) }
+attributes #1 = { "target-features"="+sve" vscale_range(1, 16) "tune-cpu"="generic" }
attributes #2 = { "target-features"="+sve" }
declare void @llvm.masked.scatter.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32*>, i32, <vscale x 4 x i1>)
diff --git a/llvm/test/Bitcode/attributes.ll b/llvm/test/Bitcode/attributes.ll
index 611871c6064bf..5a24b097beb44 100644
--- a/llvm/test/Bitcode/attributes.ll
+++ b/llvm/test/Bitcode/attributes.ll
@@ -440,13 +440,6 @@ define void @f74() vscale_range(1,0)
ret void
}
-; CHECK: define void @f75()
-; CHECK-NOT: define void @f75() #
-define void @f75() vscale_range(0,0)
-{
- ret void
-}
-
; CHECK: define void @f76(i8* swiftasync %0)
define void @f76(i8* swiftasync %0)
{
diff --git a/llvm/test/Transforms/InstCombine/icmp-vscale.ll b/llvm/test/Transforms/InstCombine/icmp-vscale.ll
index 4079577f6ca75..18f551723b5d0 100644
--- a/llvm/test/Transforms/InstCombine/icmp-vscale.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-vscale.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine -S < %s | FileCheck %s
-define i1 @ugt_vscale64_x_32() vscale_range(0,16) {
+define i1 @ugt_vscale64_x_32() vscale_range(1,16) {
; CHECK-LABEL: @ugt_vscale64_x_32(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 false
@@ -13,7 +13,7 @@ entry:
ret i1 %res
}
-define i1 @ugt_vscale64_x_31() vscale_range(0,16) {
+define i1 @ugt_vscale64_x_31() vscale_range(1,16) {
; CHECK-LABEL: @ugt_vscale64_x_31(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 false
@@ -25,7 +25,7 @@ entry:
ret i1 %res
}
-define i1 @ugt_vscale16_x_32() vscale_range(0,16) {
+define i1 @ugt_vscale16_x_32() vscale_range(1,16) {
; CHECK-LABEL: @ugt_vscale16_x_32(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 false
@@ -37,7 +37,7 @@ entry:
ret i1 %res
}
-define i1 @ult_vscale16() vscale_range(0,16) {
+define i1 @ult_vscale16() vscale_range(1,16) {
; CHECK-LABEL: @ult_vscale16(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 false
@@ -48,7 +48,7 @@ entry:
ret i1 %res
}
-define i1 @ule_vscale64() vscale_range(0,16) {
+define i1 @ule_vscale64() vscale_range(1,16) {
; CHECK-LABEL: @ule_vscale64(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 false
@@ -70,7 +70,7 @@ entry:
ret i1 %res
}
-define i1 @ne_vscale64_x_32() vscale_range(0,16) {
+define i1 @ne_vscale64_x_32() vscale_range(1,16) {
; CHECK-LABEL: @ne_vscale64_x_32(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 true
diff --git a/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll b/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
index 26fa24cec3b9a..b97a81159673c 100644
--- a/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
@@ -5,7 +5,7 @@
; Sign-extend
;
-define i32 @vscale_SExt_i8toi32() vscale_range(0, 127) {
+define i32 @vscale_SExt_i8toi32() vscale_range(1, 127) {
; CHECK-LABEL: @vscale_SExt_i8toi32(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
@@ -17,7 +17,7 @@ entry:
ret i32 %1
}
-define i32 @vscale_SExt_i8toi32_poison() vscale_range(0, 128) {
+define i32 @vscale_SExt_i8toi32_poison() vscale_range(1, 128) {
; CHECK-LABEL: @vscale_SExt_i8toi32_poison(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
@@ -34,7 +34,7 @@ define i32 @vscale_SExt_i8toi32_poison() vscale_range(0, 128) {
; Zero-extend
;
-define i32 @vscale_ZExt_i8toi32() vscale_range(0, 128) {
+define i32 @vscale_ZExt_i8toi32() vscale_range(1, 128) {
; CHECK-LABEL: @vscale_ZExt_i8toi32(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
@@ -46,7 +46,7 @@ entry:
ret i32 %1
}
-define i32 @vscale_ZExt_i8toi32_poison() vscale_range(0, 256) {
+define i32 @vscale_ZExt_i8toi32_poison() vscale_range(1, 256) {
; CHECK-LABEL: @vscale_ZExt_i8toi32_poison(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
@@ -80,7 +80,7 @@ define i32 @vscale_ZExt_i8toi32_unknown() {
; unbounded vscale_range maximum (0)
;
-define i32 @vscale_SExt_i8toi32_unbounded() vscale_range(0, 0) {
+define i32 @vscale_SExt_i8toi32_unbounded() vscale_range(1, 0) {
; CHECK-LABEL: @vscale_SExt_i8toi32_unbounded(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
@@ -93,7 +93,7 @@ define i32 @vscale_SExt_i8toi32_unbounded() vscale_range(0, 0) {
ret i32 %1
}
-define i32 @vscale_ZExt_i8toi32_unbounded() vscale_range(0, 0) {
+define i32 @vscale_ZExt_i8toi32_unbounded() vscale_range(1, 0) {
; CHECK-LABEL: @vscale_ZExt_i8toi32_unbounded(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
diff --git a/llvm/test/Transforms/InstCombine/vscale_trunc.ll b/llvm/test/Transforms/InstCombine/vscale_trunc.ll
index 040476ce558c8..c3cec9638a304 100644
--- a/llvm/test/Transforms/InstCombine/vscale_trunc.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_trunc.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
-define i8 @vscale_trunc_i32toi8() vscale_range(0, 255) {
+define i8 @vscale_trunc_i32toi8() vscale_range(1, 255) {
; CHECK-LABEL: @vscale_trunc_i32toi8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
@@ -13,7 +13,7 @@ entry:
}
-define i8 @vscale_trunc_i32toi8_poison() vscale_range(0, 256) {
+define i8 @vscale_trunc_i32toi8_poison() vscale_range(1, 256) {
; CHECK-LABEL: @vscale_trunc_i32toi8_poison(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
index f9065a6126574..4f9ae235a6153 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
@@ -100,6 +100,6 @@ for.end:
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !1}
!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
index b80b2113e2cd5..091fe92bdd438 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
@@ -552,7 +552,7 @@ for.end:
declare float @llvm.fmuladd.f32(float, float, float)
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !3, !6, !8}
!1 = distinct !{!1, !3, !7, !8}
!2 = distinct !{!2, !4, !6, !8}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
index ea9860c73f999..2c0518bbd851f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
@@ -173,4 +173,4 @@ exit:
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
index 73b9853b7171b..b08f7b9fc6b2b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
@@ -378,7 +378,7 @@ exit:
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!21 = !{!21, !22, !23}
!22 = !{!"llvm.loop.vectorize.width", i32 4}
!23 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
index 1f0453011aba7..98acd07df3384 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
@@ -117,7 +117,7 @@ for.end:
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
index a2760c79a838e..e5bbcd881163f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
@@ -153,7 +153,7 @@ for.cond.cleanup: ; preds = %for.cond.cleanup.lo
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
index 3945804d6e484..ca73ad4b060bd 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
@@ -59,7 +59,7 @@ for.end: ; preds = %for.inc, %entry
ret void
}
-attributes #0 = { "target-features"="+neon,+sve" vscale_range(0, 16) }
+attributes #0 = { "target-features"="+neon,+sve" vscale_range(1, 16) }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
index 23eb2d0b0aba0..1001a22822d9f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll
@@ -90,7 +90,7 @@ for.end: ; preds = %for.end.loopexit, %
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
index 89162d238f8cf..84fc77cedd37d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
@@ -53,7 +53,7 @@ for.end:
ret double %add
}
-attributes #0 = { "target-features"="+sve" vscale_range(0, 16) }
+attributes #0 = { "target-features"="+sve" vscale_range(1, 16) }
!0 = distinct !{!0, !1}
!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
index c7cba533fcea2..a11ac0e87b628 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
@@ -210,7 +210,7 @@ for.end: ; preds = %if.end, %for.end
ret void
}
-attributes #0 = { vscale_range(0, 16) }
+attributes #0 = { vscale_range(1, 16) }
!0 = distinct !{!0, !1, !2, !3, !4, !5}
!1 = !{!"llvm.loop.mustprogress"}
diff --git a/llvm/test/Verifier/vscale_range.ll b/llvm/test/Verifier/vscale_range.ll
index 58c1bc0127619..b85f151bcf21a 100644
--- a/llvm/test/Verifier/vscale_range.ll
+++ b/llvm/test/Verifier/vscale_range.ll
@@ -1,4 +1,7 @@
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
+; CHECK: 'vscale_range' minimum must be greater than 0
+declare i8* @a(i32*) vscale_range(0, 1)
+
; CHECK: 'vscale_range' minimum cannot be greater than maximum
declare i8* @b(i32*) vscale_range(8, 1)
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