[PATCH] D115156: [AArch64][SVE] Fix ICE extracting fixedvec from scalable load

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm marked an inline comment as done.
peterwaller-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11803
     uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
     uint64_t LoadBytes = Mem->getMemoryVT().getSizeInBits()/8;
     if (ShiftAmount == Log2_32(LoadBytes))
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paulwalker-arm wrote:
> I think the real problem is here where the code is not vector ware.  For SVE at least, the index loads are based on the scalar element type and so my feeling is that the real intent here is best followed if `getSizeInBits` becomes `getScalarSizeInBits`.
> 
> So today this function likely incorrectly always returns false for fixed length vectors, which is not great but better than the crash triggered by scalable vectors.
As discussed offline, we're concerned about the potential performance impact on other targets that we aren't able to test. So for now we're going to apply the band-aid we have.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D115156/new/

https://reviews.llvm.org/D115156