[PATCH] D115156: [AArch64][SVE] Fix ICE extracting fixedvec from scalable load

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

I've added a comment regarding what I believe is a better fix.  The problem is, following this advice may well trigger different code paths for other targets and so I'm happy to accept this more minimal fix.  I'll leave it up to you which way to go.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11803
     uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
     uint64_t LoadBytes = Mem->getMemoryVT().getSizeInBits()/8;
     if (ShiftAmount == Log2_32(LoadBytes))
----------------
I think the real problem is here where the code is not vector ware.  For SVE at least, the index loads are based on the scalar element type and so my feeling is that the real intent here is best followed if `getSizeInBits` becomes `getScalarSizeInBits`.

So today this function likely incorrectly always returns false for fixed length vectors, which is not great but better than the crash triggered by scalable vectors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115156/new/

https://reviews.llvm.org/D115156