[PATCH] D115156: [AArch64][SVE] Fix ICE extracting fixedvec from scalable load

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm created this revision.
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f526c600c043 <https://reviews.llvm.org/rGf526c600c043d9e83a359e79d617077d947c1dc3> had a concern raised because of an invalid typesize request
on a scalable vector, which this patch addresses.

Prevent shouldReduceLoadWidth from attempting to query the bit size, and
add a regression test in sve-extract-fixed-vector.ll.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115156

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll


Index: llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
+++ llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
@@ -408,6 +408,21 @@
   ret <4 x i64> %retval
 }
 
+define <4 x i32> @typesize_regression_test_v4i32(i32* %addr, i64 %idx) {
+; CHECK-LABEL: typesize_regression_test_v4i32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+entry:
+  %ptr = getelementptr inbounds i32, i32* %addr, i64 %idx
+  %bc = bitcast i32* %ptr to <vscale x 4 x i32>*
+  %ld = load <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16
+  %out = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0)
+  ret <4 x i32> %out
+}
+
 attributes #0 = { vscale_range(2,2) }
 attributes #1 = { vscale_range(8,8) }
 
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11794,6 +11794,9 @@
       Base.getOperand(1).getOpcode() == ISD::SHL &&
       Base.getOperand(1).hasOneUse() &&
       Base.getOperand(1).getOperand(1).getOpcode() == ISD::Constant) {
+    // It's unknown whether a scalable vector has a power-of-2 bitwidth.
+    if (Mem->getMemoryVT().isScalableVector())
+      return false;
     // The shift can be combined if it matches the size of the value being
     // loaded (and so reducing the width would make it not match).
     uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);


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