[PATCH] D115127: [MIPS] Add FPU Delay Slot for MIPS1/2/3

[Marko Mijalkovic via Phabricator via llvm-commits]

overdrivenpotato created this revision.
overdrivenpotato added reviewers: atanasyan, djtodoro.
Herald added subscribers: jrtc27, hiraditya, arichardson, sdardis.
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MIPS I, II, and III have delay slots for floating point comparisons and floating point register transfers (`mtc1`, `mfc1`). Currently, these are not taken into account and thus broken code may be generated on these targets. This patch inserts `nop`s as necessary, while attempting to leave the current instruction if it is safe to stay.

The tests in this patch were updated by @sajattack

Sources:

https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg01601.html
https://gcc.gnu.org/legacy-ml/gcc-patches/2003-05/msg01605.html
https://github.com/gcc-mirror/gcc/blob/16e2427f50c208dfe07d07f18009969502c25dc8/gcc/config/mips/mips.h#L1282
"See MIPS Run" Textbook: https://user-images.githubusercontent.com/1562711/144544253-de268f41-d808-4076-a500-e2cdba7f4294.png
MIPS R4000 Manual: https://user-images.githubusercontent.com/1562711/144544877-8896b4e9-3127-45a6-99d7-48b53a9b35e6.png


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115127

Files:
  llvm/lib/Target/Mips/MipsBranchExpansion.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.h
  llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll

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