[PATCH] D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:411
+    break;
+  case PPC::VMAXUD:
+  case PPC::VMAXSD:
----------------
nemanjai wrote:
> Is this just any instruction that sets `isCommutable = 1`?
Could we maybe add a comment as to why we are looking at these instructions specifically? 

I noticed that Nemanja is mostly correct in that a majority of these set `isCommutable = 1`, but with the exception of `VMULLD`, `VMULHSD`, `VMULHUD`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114800/new/

https://reviews.llvm.org/D114800