[PATCH] D114804: [RISCV] Align odd address in assemble code

[Fangrui Song via Phabricator via llvm-commits]

MaskRay added inline comments.


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Comment at: llvm/test/MC/RISCV/align-odd.s:20
+#      RV64-C-EXT-NORELAX:  0: 01 00
+# RV64-C-EXT-NORELAX-NEXT:  2: 00 00
+# RV64-C-EXT-NORELAX-NEXT:  4: 00 00
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jrtc27 wrote:
> Why a two space gap?
It will make sense when the address takes 2 digits, which can happen if the test gets more instructions. So I won't disallow two spaces here


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114804/new/

https://reviews.llvm.org/D114804