[PATCH] D114804: [RISCV] Align odd address in assemble code

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:360
 
-  if ((Count % MinNopLen) != 0)
-    return false;
+  // Align the Count to 4 (or 2 if HasStdExtC) to avoid unaligned
+  // nop instruction
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IALIGN is the architecturally-defined term for the minimum instruction alignment, and is precisely this


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Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:363
+  if (Count % MinNopLen)
+    OS.write_zeros(Count % MinNopLen);
 
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You don't need the if any more, write_zeros can happily take in 0 as the length (see AArch64 that does this, for example). Probably worth copying the comment from there too; it's also present for AMDGPU.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114804/new/

https://reviews.llvm.org/D114804