[PATCH] D114600: [CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors

[David Sherwood via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG84364bdaabfc: [CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors (authored by david-arm).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114600/new/

https://reviews.llvm.org/D114600

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll


Index: llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
===================================================================
--- llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
+++ llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
@@ -40,4 +40,24 @@
   ret <8 x i16> %shuffle
 }
 
+
+; The concat_vectors operation in this test is introduced when splitting
+; the fptrunc operation due to the split <vscale x 4 x double> input operand.
+define void @test_concat_fptrunc_v4f64_to_v4f32(<vscale x 4 x float>* %ptr) #1 {
+entry:
+; CHECK-LABEL: test_concat_fptrunc_v4f64_to_v4f32:
+; CHECK:       fmov    z0.d, #1.00000000
+; CHECK-NEXT:  ptrue   p0.d
+; CHECK-NEXT:  fcvt    z0.s, p0/m, z0.d
+; CHECK-NEXT:  ptrue   p0.s
+; CHECK-NEXT:  uzp1    z0.s, z0.s, z0.s
+; CHECK-NEXT:  st1w    { z0.s }, p0, [x0]
+; CHECK-NEXT:  ret
+  %0 = shufflevector <vscale x 4 x double> insertelement (<vscale x 4 x double> poison, double 1.000000e+00, i32 0), <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %1 = fptrunc <vscale x 4 x double> %0 to <vscale x 4 x float>
+  store <vscale x 4 x float> %1, <vscale x 4 x float>* %ptr, align 4
+  ret void
+}
+
 attributes #0 = { nounwind }
+attributes #1 = { "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14109,6 +14109,9 @@
   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
   unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
 
+  if (VT.isScalableVector())
+    return SDValue();
+
   // Optimize concat_vectors of truncated vectors, where the intermediate
   // type is illegal, to avoid said illegality,  e.g.,
   //   (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),


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