[PATCH] D110076: [AMDGPU][GlobalISel] Code quality: Combine V_RSQ

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp:217
+    MachineInstr *DivSrcMI = nullptr;
+    mi_match(MI.getOperand(0).getReg(), MRI,
+             m_GFDiv(m_SpecificICst(1), m_MInstr(DivSrcMI)));
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I still think it's wrong to handle G_FDIV here.
- it's unnecessary, because we are running post-legalizer and G_FDIV will always get legalized to something else.
- even if G_FDIV **did** appear here, I don't think it should be combined into an rsq instruction without checking for all the fast/unsafe math flags, like in AMDGPULegalizerInfo::legalizeFastUnsafeFDIV.

I think we just need an **IR** test to check that `fdiv float 1.0, %x1` with appropriate fast math flags get combined with `@llvm.fsqrt` to generate a v_rsq instruction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110076/new/

https://reviews.llvm.org/D110076