[PATCH] D114405: Optimize shift and accumulate pattern in AArch64.

[Xin Tong via Phabricator via llvm-commits]

adriantong1024 added a comment.

In D114405#3148242 <https://reviews.llvm.org/D114405#3148242>, @dmgreen wrote:

> Could this be handled with a tablegen pattern? Something like the or_is_add pattern from X86 (but using haveNoCommonBitsSet). Maybe a PatFrag that accepts an add or an add-like-or?

Thanks for the comment David. I will take a look at handling in tablegen pattern as well. Will update when I have more.

> Also should ssra be treated the same way?




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https://reviews.llvm.org/D114405