[PATCH] D114405: Optimize shift and accumulate pattern in AArch64.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Could this be handled with a tablegen pattern? Something like the or_is_add pattern from X86 (but using haveNoCommonBitsSet). Maybe a PatFrag that accepts an add or an add-like-or?

Also should ssra be treated the same way?



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Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:12
+  %4 = lshr <8 x i16> %3, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+  %5 = or <8 x i16> %4, %3
+  %6 = bitcast <8 x i16> %5 to <16 x i8>
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It's probably a better test to return the %5, not extract a single lane from it.


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https://reviews.llvm.org/D114405