[PATCH] D114449: [ARM] Make v2i1 legal

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: simon_tatham, samtebbs, SjoerdMeijer, miyuki.
Herald added subscribers: armkevincheng, jsmolens, eric-k256, hiraditya, kristof.beyls, qcolombet.
Herald added a reviewer: sjarus.
dmgreen requested review of this revision.
Herald added a project: LLVM.

MVE can treat v16i1, v8i1, v4i1 and v2i1 as different views onto the same 16bit VPR.P0 register, with v2i1 holding two 8 bit values for the two halves. This was never treated as a legal type in llvm in the past as there are not many 64bit instructions and no 64bit compares. There are a few instructions that could use it though, notably a VSELECT (as it can handle any size using the underlying v16i8 VPSEL), AND/OR/XOR for similar reasons, some gathers/scatter and long multiplies and VCTP64 instructions.

This patch goes through and makes v2i1 a legal type, handling all the cases that fall out of that. It also makes VSELECT legal for v2i64 as a side benefit. A lot of the codegen changes as a result - usually in way that is a little better or a little worse, but still expensive. Costs can change a little too in the process, again in a way that expensive things remain expensive. A lot of the tests that changed are mainly to ensure correctness - the code can hopefully be improved in the future where it comes up in practice.

The intrinsics currently remain using the v4i1 they previously did to emulate a v2i1. This will be changed in a followup patch but this one was already large enough.


https://reviews.llvm.org/D114449

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
  llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
  llvm/test/Analysis/CostModel/ARM/arith-usat.ll
  llvm/test/Analysis/CostModel/ARM/mve-abs.ll
  llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
  llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
  llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
  llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
  llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
  llvm/test/Analysis/CostModel/ARM/select.ll
  llvm/test/CodeGen/Thumb2/active_lane_mask.ll
  llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
  llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
  llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
  llvm/test/CodeGen/Thumb2/mve-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-masked-store.ll
  llvm/test/CodeGen/Thumb2/mve-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
  llvm/test/CodeGen/Thumb2/mve-pred-and.ll
  llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
  llvm/test/CodeGen/Thumb2/mve-pred-const.ll
  llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
  llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
  llvm/test/CodeGen/Thumb2/mve-pred-not.ll
  llvm/test/CodeGen/Thumb2/mve-pred-or.ll
  llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
  llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
  llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
  llvm/test/CodeGen/Thumb2/mve-vabdus.ll
  llvm/test/CodeGen/Thumb2/mve-vcmp.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
  llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
  llvm/test/CodeGen/Thumb2/mve-vpsel.ll
  llvm/test/CodeGen/Thumb2/mve-vqmovn.ll
  llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
  llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll