[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-punpklo-combine.ll:28
+
+define <vscale x 8 x i16> @masked_load_sext_i8i16_pture_vl(i8* %ap, i8* %bp) #0 {
+; CHECK-LABEL: masked_load_sext_i8i16_pture_vl:
----------------
ptrue


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221