[PATCH] D113914: [X86][Costmodel] `*ext v64i1 to v32i16` can appear after legalization, cost is same as for `*ext v32i1 to v32i16`

[Roman Lebedev via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2037ec725ff2: [X86][Costmodel] `*ext v64i1 to v32i16` can appear after legalization, cost is… (authored by lebedev.ri).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113914/new/

https://reviews.llvm.org/D113914

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/extend.ll


Index: llvm/test/Analysis/CostModel/X86/extend.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/extend.ll
+++ llvm/test/Analysis/CostModel/X86/extend.ll
@@ -675,8 +675,8 @@
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = zext <16 x i1> undef to <16 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V64i16 = zext <64 x i1> undef to <64 x i16>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V128i16 = zext <128 x i1> undef to <128 x i16>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V64i16 = zext <64 x i1> undef to <64 x i16>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V128i16 = zext <128 x i1> undef to <128 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %I8 = zext i1 undef to i8
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = zext <2 x i1> undef to <2 x i8>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = zext <4 x i1> undef to <4 x i8>
@@ -1439,8 +1439,8 @@
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = sext <8 x i1> undef to <8 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = sext <16 x i1> undef to <16 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V64i16 = sext <64 x i1> undef to <64 x i16>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V128i16 = sext <128 x i1> undef to <128 x i16>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V64i16 = sext <64 x i1> undef to <64 x i16>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V128i16 = sext <128 x i1> undef to <128 x i16>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %I8 = sext i1 undef to i8
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V2i8 = sext <2 x i1> undef to <2 x i8>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4i8 = sext <4 x i1> undef to <4 x i8>
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1594,6 +1594,7 @@
     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
     { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1, 1 },
     { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
+    { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 },
     { ISD::SIGN_EXTEND, MVT::v64i8,  MVT::v64i1, 1 },
 
     // Mask zero extend is a sext + shift.
@@ -1607,6 +1608,7 @@
     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
     { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },
     { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
+    { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 },
     { ISD::ZERO_EXTEND, MVT::v64i8,  MVT::v64i1, 2 },
 
     { ISD::TRUNCATE,    MVT::v32i8,  MVT::v32i16, 2 },


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