[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Though, I'm unconvinced about whether the hazard in the epilogue matters in practice. In a simple in-order micoarchitecture if restoring ra stalls then it doesn't matter where that is, you can't execute out-of-order. In a superscalar core you'll just speculate past the ret anyway, which should predict accurately for anything with a half-decent RAS, though I guess you'll have unresolved speculation for longer that might be an issue. Is there a particular microarchitecture you've measured an appreciable difference for this on?


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