[PATCH] D113970: [SelectionDAG] Add pattern to haveNoCommonBitsSet.

[Omer Aviram via Phabricator via llvm-commits]

OmerAviram updated this revision to Diff 387618.
OmerAviram added a comment.
Herald added a subscriber: pengfei.

Added ll test for X86 Target.
prior to the patch, the ir included an or instruction:

  ; CHECK-NEXT:    andl %esi, %edx
  ; CHECK-NEXT:    notl %esi
  ; CHECK-NEXT:    andl %edi, %esi
  ; CHECK-NEXT:    orl %edx, %esi
  ; CHECK-NEXT:    leal 1(%rsi), %eax

After the patch, the or instruction can be combined into an add, since the operands have no common bits.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113970/new/

https://reviews.llvm.org/D113970

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/X86/or-lea.ll


Index: llvm/test/CodeGen/X86/or-lea.ll
===================================================================
--- llvm/test/CodeGen/X86/or-lea.ll
+++ llvm/test/CodeGen/X86/or-lea.ll
@@ -131,3 +131,24 @@
   ret i64 %or
 }
 
+; In the following pattern, lhs and rhs of the or instruction have no common bits.
+
+define i16 @or_and_not_and(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: or_and_not_and:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
+; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:    andl %esi, %edx
+; CHECK-NEXT:    notl %esi
+; CHECK-NEXT:    andl %edi, %esi
+; CHECK-NEXT:    leal 1(%rdx,%rsi), %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retq
+entry:
+  %and1 = and i16 %z, %y
+  %xor = xor i16 %y, -1
+  %and2 = and i16 %x, %xor
+  %or = or i16 %and1, %and2
+  %inc = add i16 %or, 1
+  ret i16 %inc
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4539,11 +4539,28 @@
   return false;
 }
 
+static bool matchNoCommonBitsPattern(SDValue A, SDValue B) {
+  if (isBitwiseNot(A, true)) {
+    SDValue NotOperand = A->getOperand(0);
+    assert(B->getOpcode() == ISD::AND && "Expected AND opcode!");
+    if (NotOperand == B->getOperand(0) || NotOperand == B->getOperand(1))
+      return true;
+  }
+  return false;
+}
+
 // FIXME: unify with llvm::haveNoCommonBitsSet.
-// FIXME: could also handle masked merge pattern (X & ~M) op (Y & M)
 bool SelectionDAG::haveNoCommonBitsSet(SDValue A, SDValue B) const {
   assert(A.getValueType() == B.getValueType() &&
          "Values must have the same type");
+  // Match masked merge pattern (X & ~M) op (Y & M)
+  if (A->getOpcode() == ISD::AND && B->getOpcode() == ISD::AND) {
+    if (matchNoCommonBitsPattern(A->getOperand(0), B) ||
+        matchNoCommonBitsPattern(A->getOperand(1), B) ||
+        matchNoCommonBitsPattern(B->getOperand(0), A) ||
+        matchNoCommonBitsPattern(B->getOperand(1), A))
+      return true;
+  }
   return KnownBits::haveNoCommonBitsSet(computeKnownBits(A),
                                         computeKnownBits(B));
 }


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