[PATCH] D113959: [llvm][RISC-V] Use floating-point ABI by default if possible
Oi Chee Cheung via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 15 17:45:28 PST 2021
occheung created this revision.
occheung added a reviewer: asb.
occheung added a project: LLVM.
Herald added subscribers: VincentWu, luke957, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, qcolombet.
occheung requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
This patch makes changes to the default ABI for RISC-V targets.
Before patch, only integer ABI (ilp32e, ilp32, lp64) can be selected **by default** (without passing ABIName in MCOptions).
After patch, ilp32f/d and lp64f/d can be selected if F/D extensions are detected.
Tests are updated by adding specifying target-abi if necessary.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D113959
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
llvm/test/CodeGen/RISCV/calling-conv-half.ll
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/double-br-fcmp.ll
llvm/test/CodeGen/RISCV/double-calling-conv.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
llvm/test/CodeGen/RISCV/fastcc-float.ll
llvm/test/CodeGen/RISCV/float-arith.ll
llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/float-br-fcmp.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/float-fcmp.ll
llvm/test/CodeGen/RISCV/float-imm.ll
llvm/test/CodeGen/RISCV/float-intrinsics.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/float-select-fcmp.ll
llvm/test/CodeGen/RISCV/fpenv.ll
llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/select-sra.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
llvm/test/CodeGen/RISCV/select-const.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
llvm/test/CodeGen/RISCV/vararg.ll
llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll
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