[PATCH] D113192: [DAG] MatchRotate - support rotate-by-constant of illegal types

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64zbp.ll:1863
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    greviw a0, a0, 16
+; RV64ZBP-NEXT:    roriw a0, a0, 16
 ; RV64ZBP-NEXT:    ret
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RKSimon wrote:
> @craig.topper Is this change OK? The test is called grev16_32 and neither target generates a grev op.
I think it is ok. It's now matches grev16_i32_fshl and grev16_i32_fshr which are the same as this using intrinsics instead of shifts and or.

Our assumption was that a rotate would be at least as good as a grev instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113192/new/

https://reviews.llvm.org/D113192