[PATCH] D113827: [X86] Enable use of 128/256-bit VPTERNLOG on non-VLX targets

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: pengfei, craig.topper.
Herald added a subscriber: hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Similar to what we've done for other ops, this patch widens VPTERNLOG to a 512-bit op for non-VLX targets.

Widening prevents folding of entire vector loads, so I've extended getAVX512Node to try to more aggressively create broadcastable constants for folding, I've refactored getAVX512Node so that VLX targets can make better use of this as well.

Fixes regressions in D113192 <https://reviews.llvm.org/D113192>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113827

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avx512fp16-arith.ll
  llvm/test/CodeGen/X86/combine-bitselect.ll
  llvm/test/CodeGen/X86/min-legal-vector-width.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll

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