[PATCH] D113805: [RISCV] Improve codegen for i32 udiv/urem by constant on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoM.td:112
 // zeroing the upper 32 bits.
 // TODO: If one of the operands is zero extended and the other isn't, we might
 // still be better off shifting both left by 32.
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mcberg2021 wrote:
> Looks like the TODO is done making that part of the comment no longer needed
I think when I wrote the TODO I meant to add something like these patterns

`(i64 (mul (and GPR:$rs1, 0xffffffff), (assertzexti32 GPR:$rs2)))`

and

`(i64 (mul (assertzexti32 GPR:$rs1), (and GPR:$rs2, 0xffffffff)))`

Where assertzexti32 covers AssertZExt and anything that computeKnownBits can prove is has only 32 active bits. In that case we'd insert a SLLI on the assertexti32 side without reducing any instructions for that operand. If that operand is the critical path it would make it worse. If the AND has an additional use it would be an increase in code size.

SelectionDAG doesn't normally check the critical path like that, so maybe I should drop the TODO based on the fact that we couldn't check that.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113805/new/

https://reviews.llvm.org/D113805