[PATCH] D113805: [RISCV] Improve codegen for i32 udiv/urem by constant on RV64.

[Michael Berg via Phabricator via llvm-commits]

mcberg2021 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoM.td:112
 // zeroing the upper 32 bits.
 // TODO: If one of the operands is zero extended and the other isn't, we might
 // still be better off shifting both left by 32.
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Looks like the TODO is done making that part of the comment no longer needed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113805/new/

https://reviews.llvm.org/D113805