[llvm] ce89335 - [x86] add tests and RUNs for vector compares; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 11 11:21:01 PST 2021
Author: Sanjay Patel
Date: 2021-11-11T14:18:25-05:00
New Revision: ce89335fe8c97ed91806cd57a0c425acc48b2f18
URL: https://github.com/llvm/llvm-project/commit/ce89335fe8c97ed91806cd57a0c425acc48b2f18
DIFF: https://github.com/llvm/llvm-project/commit/ce89335fe8c97ed91806cd57a0c425acc48b2f18.diff
LOG: [x86] add tests and RUNs for vector compares; NFC
More coverage for D113603
Added:
Modified:
llvm/test/CodeGen/X86/vector-pcmp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/vector-pcmp.ll b/llvm/test/CodeGen/X86/vector-pcmp.ll
index fc5b86a752ca..fbfac84f6332 100644
--- a/llvm/test/CodeGen/X86/vector-pcmp.ll
+++ b/llvm/test/CodeGen/X86/vector-pcmp.ll
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE42
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512DQBW
; Lower common integer comparisons such as 'isPositive' efficiently:
; https://llvm.org/bugs/show_bug.cgi?id=26701
@@ -120,6 +122,12 @@ define <32 x i8> @test_pcmpgtb_256(<32 x i8> %x) {
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_pcmpgtb_256:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sign = ashr <32 x i8> %x, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%not = xor <32 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
ret <32 x i8> %not
@@ -149,6 +157,12 @@ define <16 x i16> @test_pcmpgtw_256(<16 x i16> %x) {
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_pcmpgtw_256:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sign = ashr <16 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%not = xor <16 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
ret <16 x i16> %not
@@ -178,6 +192,12 @@ define <8 x i32> @test_pcmpgtd_256(<8 x i32> %x) {
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_pcmpgtd_256:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sign = ashr <8 x i32> %x, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%not = xor <8 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
ret <8 x i32> %not
@@ -217,6 +237,12 @@ define <4 x i64> @test_pcmpgtq_256(<4 x i64> %x) {
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_pcmpgtq_256:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sign = ashr <4 x i64> %x, <i64 63, i64 63, i64 63, i64 63>
%not = xor <4 x i64> %sign, <i64 -1, i64 -1, i64 -1, i64 -1>
ret <4 x i64> %not
@@ -263,6 +289,12 @@ define <16 x i16> @cmpeq_zext_v16i16(<16 x i16> %a, <16 x i16> %b) {
; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlw $15, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpeq_zext_v16i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpsrlw $15, %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp eq <16 x i16> %a, %b
%zext = zext <16 x i1> %cmp to <16 x i16>
ret <16 x i16> %zext
@@ -322,6 +354,12 @@ define <4 x i64> @cmpeq_zext_v4i64(<4 x i64> %a, <4 x i64> %b) {
; AVX2-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlq $63, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpeq_zext_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpsrlq $63, %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp eq <4 x i64> %a, %b
%zext = zext <4 x i1> %cmp to <4 x i64>
ret <4 x i64> %zext
@@ -352,6 +390,12 @@ define <32 x i8> @cmpgt_zext_v32i8(<32 x i8> %a, <32 x i8> %b) {
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpgt_zext_v32i8:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <32 x i8> %a, %b
%zext = zext <32 x i1> %cmp to <32 x i8>
ret <32 x i8> %zext
@@ -398,6 +442,12 @@ define <8 x i32> @cmpgt_zext_v8i32(<8 x i32> %a, <8 x i32> %b) {
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrld $31, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpgt_zext_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpsrld $31, %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <8 x i32> %a, %b
%zext = zext <8 x i1> %cmp to <8 x i32>
ret <8 x i32> %zext
@@ -471,6 +521,12 @@ define <8 x i32> @cmpne_knownzeros_zext_v8i16_v8i32(<8 x i16> %x) {
; AVX2-NEXT: vpsrlw $15, %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpne_knownzeros_zext_v8i16_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsrlw $15, %xmm0, %xmm0
+; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512-NEXT: retq
%a = lshr <8 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%b = icmp ne <8 x i16> %a, zeroinitializer
%c = zext <8 x i1> %b to <8 x i32>
@@ -496,6 +552,11 @@ define <8 x i32> @cmpne_knownzeros_zext_v8i32_v8i32(<8 x i32> %x) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrld $31, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpne_knownzeros_zext_v8i32_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsrld $31, %ymm0, %ymm0
+; AVX512-NEXT: retq
%a = lshr <8 x i32> %x, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%b = icmp ne <8 x i32> %a, zeroinitializer
%c = zext <8 x i1> %b to <8 x i32>
@@ -533,6 +594,13 @@ define <8 x i16> @cmpne_knownzeros_zext_v8i32_v8i16(<8 x i32> %x) {
; AVX2-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: cmpne_knownzeros_zext_v8i32_v8i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsrld $31, %ymm0, %ymm0
+; AVX512-NEXT: vpmovdw %ymm0, %xmm0
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: retq
%a = lshr <8 x i32> %x, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%b = icmp ne <8 x i32> %a, zeroinitializer
%c = zext <8 x i1> %b to <8 x i16>
@@ -681,6 +749,13 @@ define <4 x i64> @not_signbit_mask_v4i64(<4 x i64> %x, <4 x i64> %y) {
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: not_signbit_mask_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: retq
%sh = ashr <4 x i64> %x, <i64 63, i64 63, i64 63, i64 63>
%not = xor <4 x i64> %sh, <i64 -1, i64 -1, i64 -1, i64 -1>
%and = and <4 x i64> %y, %not
@@ -712,6 +787,13 @@ define <8 x i32> @not_signbit_mask_v8i32(<8 x i32> %x, <8 x i32> %y) {
; AVX2-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: not_signbit_mask_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sh = ashr <8 x i32> %x, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%not = xor <8 x i32> %sh, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%and = and <8 x i32> %not, %y
@@ -743,6 +825,13 @@ define <16 x i16> @not_signbit_mask_v16i16(<16 x i16> %x, <16 x i16> %y) {
; AVX2-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: not_signbit_mask_v16i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: retq
%sh = ashr <16 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%not = xor <16 x i16> %sh, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%and = and <16 x i16> %y, %not
@@ -775,6 +864,13 @@ define <32 x i8> @not_signbit_mask_v32i8(<32 x i8> %x, <32 x i8> %y) {
; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: not_signbit_mask_v32i8:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%sh = ashr <32 x i8> %x, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%not = xor <32 x i8> %sh, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%and = and <32 x i8> %not, %y
@@ -906,6 +1002,13 @@ define <4 x i64> @is_positive_mask_v4i64(<4 x i64> %x, <4 x i64> %y) {
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
%mask = sext <4 x i1> %cmp to <4 x i64>
%and = and <4 x i64> %mask, %y
@@ -938,6 +1041,13 @@ define <8 x i32> @is_positive_mask_v8i32(<8 x i32> %x, <8 x i32> %y) {
; AVX2-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <8 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%mask = sext <8 x i1> %cmp to <8 x i32>
%and = and <8 x i32> %y, %mask
@@ -970,6 +1080,13 @@ define <16 x i16> @is_positive_mask_v16i16(<16 x i16> %x, <16 x i16> %y) {
; AVX2-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_v16i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <16 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%mask = sext <16 x i1> %cmp to <16 x i16>
%and = and <16 x i16> %mask, %y
@@ -1002,6 +1119,13 @@ define <32 x i8> @is_positive_mask_v32i8(<32 x i8> %x, <32 x i8> %y) {
; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_v32i8:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <32 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%mask = sext <32 x i1> %cmp to <32 x i8>
%and = and <32 x i8> %y, %mask
@@ -1137,6 +1261,13 @@ define <4 x i64> @is_positive_mask_load_v4i64(<4 x i64> %x, <4 x i64>* %p) {
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand (%rdi), %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_load_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpand (%rdi), %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
%mask = sext <4 x i1> %cmp to <4 x i64>
%y = load <4 x i64>, <4 x i64>* %p
@@ -1170,6 +1301,13 @@ define <8 x i32> @is_positive_mask_load_v8i32(<8 x i32> %x, <8 x i32>* %p) {
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand (%rdi), %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_load_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpand (%rdi), %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <8 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%mask = sext <8 x i1> %cmp to <8 x i32>
%y = load <8 x i32>, <8 x i32>* %p
@@ -1203,6 +1341,13 @@ define <16 x i16> @is_positive_mask_load_v16i16(<16 x i16> %x, <16 x i16>* %p) {
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand (%rdi), %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_load_v16i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpand (%rdi), %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <16 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%mask = sext <16 x i1> %cmp to <16 x i16>
%y = load <16 x i16>, <16 x i16>* %p
@@ -1236,9 +1381,546 @@ define <32 x i8> @is_positive_mask_load_v32i8(<32 x i8> %x, <32 x i8>* %p) {
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand (%rdi), %ymm0, %ymm0
; AVX2-NEXT: retq
+;
+; AVX512-LABEL: is_positive_mask_load_v32i8:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpand (%rdi), %ymm0, %ymm0
+; AVX512-NEXT: retq
%cmp = icmp sgt <32 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%mask = sext <32 x i1> %cmp to <32 x i8>
%y = load <32 x i8>, <32 x i8>* %p
%and = and <32 x i8> %y, %mask
ret <32 x i8> %and
}
+
+define <2 x i1> @ispositive_mask_v2i64_v2i1(<2 x i64> %x, <2 x i1> %y) {
+; SSE2-LABEL: ispositive_mask_v2i64_v2i1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
+; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: ispositive_mask_v2i64_v2i1:
+; SSE42: # %bb.0:
+; SSE42-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE42-NEXT: pcmpgtq %xmm2, %xmm0
+; SSE42-NEXT: pand %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: ispositive_mask_v2i64_v2i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: ispositive_mask_v2i64_v2i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: ispositive_mask_v2i64_v2i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpsllq $63, %xmm1, %xmm1
+; AVX512F-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX512F-NEXT: vpcmpgtq %xmm2, %xmm0, %k1
+; AVX512F-NEXT: vptestmq %xmm1, %xmm1, %k1 {%k1}
+; AVX512F-NEXT: vmovdqa64 %xmm2, %xmm0 {%k1} {z}
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: ispositive_mask_v2i64_v2i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllq $63, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512DQBW-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX512DQBW-NEXT: vpcmpgtq %xmm3, %xmm0, %k1
+; AVX512DQBW-NEXT: vpcmpgtq %xmm1, %xmm2, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2q %k0, %xmm0
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <2 x i64> %x, <i64 -1, i64 -1>
+ %and = and <2 x i1> %cmp, %y
+ ret <2 x i1> %and
+}
+
+define <4 x i1> @is_positive_mask_v4i32_v4i1(<4 x i32> %x, <4 x i1> %y) {
+; SSE-LABEL: is_positive_mask_v4i32_v4i1:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pcmpgtd %xmm2, %xmm0
+; SSE-NEXT: pand %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v4i32_v4i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v4i32_v4i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v4i32_v4i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
+; AVX512F-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX512F-NEXT: vpcmpgtd %xmm2, %xmm0, %k1
+; AVX512F-NEXT: vptestmd %xmm1, %xmm1, %k1 {%k1}
+; AVX512F-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1} {z}
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v4i32_v4i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpslld $31, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpmovd2m %xmm1, %k1
+; AVX512DQBW-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2d %k0, %xmm0
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %and = and <4 x i1> %y, %cmp
+ ret <4 x i1> %and
+}
+
+define <8 x i1> @is_positive_mask_v8i16_v8i1(<8 x i16> %x, <8 x i1> %y) {
+; SSE-LABEL: is_positive_mask_v8i16_v8i1:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pcmpgtw %xmm2, %xmm0
+; SSE-NEXT: pand %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v8i16_v8i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtw %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v8i16_v8i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtw %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v8i16_v8i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX512F-NEXT: vpcmpgtw %xmm2, %xmm0, %xmm0
+; AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v8i16_v8i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllw $15, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512DQBW-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX512DQBW-NEXT: vpcmpgtw %xmm3, %xmm0, %k1
+; AVX512DQBW-NEXT: vpcmpgtw %xmm1, %xmm2, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2w %k0, %xmm0
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %and = and <8 x i1> %cmp, %y
+ ret <8 x i1> %and
+}
+
+define <16 x i1> @is_positive_mask_v16i8_v16i1(<16 x i8> %x, <16 x i1> %y) {
+; SSE-LABEL: is_positive_mask_v16i8_v16i1:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pcmpgtb %xmm2, %xmm0
+; SSE-NEXT: pand %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v16i8_v16i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v16i8_v16i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v16i8_v16i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX512F-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0
+; AVX512F-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v16i8_v16i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllw $7, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpmovb2m %xmm1, %k1
+; AVX512DQBW-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2b %k0, %xmm0
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %and = and <16 x i1> %y, %cmp
+ ret <16 x i1> %and
+}
+
+define <4 x i1> @is_positive_mask_v4i64_v4i1(<4 x i64> %x, <4 x i1> %y) {
+; SSE2-LABEL: is_positive_mask_v4i64_v4i1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
+; SSE2-NEXT: pand %xmm2, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: is_positive_mask_v4i64_v4i1:
+; SSE42: # %bb.0:
+; SSE42-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE42-NEXT: pcmpgtq %xmm3, %xmm1
+; SSE42-NEXT: pcmpgtq %xmm3, %xmm0
+; SSE42-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; SSE42-NEXT: andps %xmm2, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v4i64_v4i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v4i64_v4i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX2-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v4i64_v4i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
+; AVX512F-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512F-NEXT: vpcmpgtq %ymm2, %ymm0, %k1
+; AVX512F-NEXT: vptestmd %xmm1, %xmm1, %k1 {%k1}
+; AVX512F-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v4i64_v4i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpslld $31, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512DQBW-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
+; AVX512DQBW-NEXT: vpcmpgtq %ymm3, %ymm0, %k1
+; AVX512DQBW-NEXT: vpcmpgtd %xmm1, %xmm2, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2d %k0, %xmm0
+; AVX512DQBW-NEXT: vzeroupper
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
+ %and = and <4 x i1> %cmp, %y
+ ret <4 x i1> %and
+}
+
+define <8 x i1> @is_positive_mask_v8i32_v8i1(<8 x i32> %x, <8 x i1> %y) {
+; SSE-LABEL: is_positive_mask_v8i32_v8i1:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pcmpgtd %xmm3, %xmm0
+; SSE-NEXT: packssdw %xmm1, %xmm0
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v8i32_v8i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtd %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v8i32_v8i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX2-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX2-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v8i32_v8i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512F-NEXT: vpslld $31, %ymm1, %ymm1
+; AVX512F-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512F-NEXT: vpcmpgtd %ymm2, %ymm0, %k1
+; AVX512F-NEXT: vptestmd %ymm1, %ymm1, %k1 {%k1}
+; AVX512F-NEXT: vmovdqa32 %ymm2, %ymm0 {%k1} {z}
+; AVX512F-NEXT: vpmovdw %ymm0, %xmm0
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v8i32_v8i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllw $15, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpmovw2m %xmm1, %k1
+; AVX512DQBW-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512DQBW-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2w %k0, %xmm0
+; AVX512DQBW-NEXT: vzeroupper
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <8 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+ %and = and <8 x i1> %y, %cmp
+ ret <8 x i1> %and
+}
+
+define <16 x i1> @is_positive_mask_v16i16_v16i1(<16 x i16> %x, <16 x i1> %y) {
+; SSE-LABEL: is_positive_mask_v16i16_v16i1:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: pcmpgtw %xmm3, %xmm1
+; SSE-NEXT: pcmpgtw %xmm3, %xmm0
+; SSE-NEXT: packsswb %xmm1, %xmm0
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v16i16_v16i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtw %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v16i16_v16i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX2-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v16i16_v16i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm1
+; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1
+; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1
+; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
+; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 {%k1}
+; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
+; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v16i16_v16i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllw $7, %xmm1, %xmm1
+; AVX512DQBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512DQBW-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
+; AVX512DQBW-NEXT: vpcmpgtw %ymm3, %ymm0, %k1
+; AVX512DQBW-NEXT: vpcmpgtb %xmm1, %xmm2, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2b %k0, %xmm0
+; AVX512DQBW-NEXT: vzeroupper
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <16 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %and = and <16 x i1> %cmp, %y
+ ret <16 x i1> %and
+}
+
+define <32 x i1> @is_positive_mask_v32i8_v32i1(<32 x i8> %x, <32 x i1> %y) {
+; SSE2-LABEL: is_positive_mask_v32i8_v32i1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq %rdi, %rax
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3],xmm5[4],xmm2[4],xmm5[5],xmm2[5],xmm5[6],xmm2[6],xmm5[7],xmm2[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT: movd %r9d, %xmm4
+; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3],xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-NEXT: movd %r8d, %xmm2
+; SSE2-NEXT: movd %ecx, %xmm3
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT: movd %edx, %xmm6
+; SSE2-NEXT: movd %esi, %xmm2
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm6[0],xmm2[1],xmm6[1],xmm2[2],xmm6[2],xmm2[3],xmm6[3],xmm2[4],xmm6[4],xmm2[5],xmm6[5],xmm2[6],xmm6[6],xmm2[7],xmm6[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3],xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm6 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1],xmm6[2],xmm3[2],xmm6[3],xmm3[3],xmm6[4],xmm3[4],xmm6[5],xmm3[5],xmm6[6],xmm3[6],xmm6[7],xmm3[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3],xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE2-NEXT: movd {{.*#+}} xmm7 = mem[0],zero,zero,zero
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm3[0],xmm7[1],xmm3[1],xmm7[2],xmm3[2],xmm7[3],xmm3[3],xmm7[4],xmm3[4],xmm7[5],xmm3[5],xmm7[6],xmm3[6],xmm7[7],xmm3[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm4[0],xmm7[1],xmm4[1],xmm7[2],xmm4[2],xmm7[3],xmm4[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm6[0]
+; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm0
+; SSE2-NEXT: pand %xmm2, %xmm0
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm1
+; SSE2-NEXT: pand %xmm7, %xmm1
+; SSE2-NEXT: psllw $7, %xmm1
+; SSE2-NEXT: pmovmskb %xmm1, %ecx
+; SSE2-NEXT: shll $16, %ecx
+; SSE2-NEXT: psllw $7, %xmm0
+; SSE2-NEXT: pmovmskb %xmm0, %edx
+; SSE2-NEXT: orl %ecx, %edx
+; SSE2-NEXT: movl %edx, (%rdi)
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: is_positive_mask_v32i8_v32i1:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: movd %esi, %xmm2
+; SSE42-NEXT: pinsrb $1, %edx, %xmm2
+; SSE42-NEXT: pinsrb $2, %ecx, %xmm2
+; SSE42-NEXT: pinsrb $3, %r8d, %xmm2
+; SSE42-NEXT: pinsrb $4, %r9d, %xmm2
+; SSE42-NEXT: pinsrb $5, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; SSE42-NEXT: pinsrb $1, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $2, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $3, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $4, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $5, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE42-NEXT: pcmpgtb %xmm4, %xmm1
+; SSE42-NEXT: pand %xmm3, %xmm1
+; SSE42-NEXT: pcmpgtb %xmm4, %xmm0
+; SSE42-NEXT: pand %xmm2, %xmm0
+; SSE42-NEXT: psllw $7, %xmm0
+; SSE42-NEXT: pmovmskb %xmm0, %ecx
+; SSE42-NEXT: psllw $7, %xmm1
+; SSE42-NEXT: pmovmskb %xmm1, %edx
+; SSE42-NEXT: shll $16, %edx
+; SSE42-NEXT: orl %ecx, %edx
+; SSE42-NEXT: movl %edx, (%rdi)
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: is_positive_mask_v32i8_v32i1:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: is_positive_mask_v32i8_v32i1:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: is_positive_mask_v32i8_v32i1:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
+; AVX512F-NEXT: vpand %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: retq
+;
+; AVX512DQBW-LABEL: is_positive_mask_v32i8_v32i1:
+; AVX512DQBW: # %bb.0:
+; AVX512DQBW-NEXT: vpsllw $7, %ymm1, %ymm1
+; AVX512DQBW-NEXT: vpmovb2m %ymm1, %k1
+; AVX512DQBW-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512DQBW-NEXT: vpcmpgtb %ymm1, %ymm0, %k0 {%k1}
+; AVX512DQBW-NEXT: vpmovm2b %k0, %ymm0
+; AVX512DQBW-NEXT: retq
+ %cmp = icmp sgt <32 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ %and = and <32 x i1> %y, %cmp
+ ret <32 x i1> %and
+}
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