[PATCH] D113543: [RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 11 07:21:39 PST 2021


frasercrmck added a comment.

To what extent is this generic code that other targets would benefit from?

I'm also not the most comfortable with floating-point. I was wondering if we could prove these transformations with https://alive2.llvm.org/ce/. I tried something simple but it doesn't recognize `copysign`. That's not to say it's impossible to express that operation in another way, but it's cumbersome.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1665
+  SDValue Setcc = DAG.getSetCC(DL, SetccVT, Abs, MaxValNode, ISD::SETOLT);
+  return DAG.getSelect(DL, VT, Setcc, Truncated, Op.getOperand(0));
+}
----------------
Can use `Src` here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113543/new/

https://reviews.llvm.org/D113543



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