[PATCH] D113655: [IR] Allow all integer types for stepvector intrinsic

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-stepvector.ll:50
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    index z0.d, #0, #1
+; CHECK-NEXT:    ret
----------------
sdesmalen wrote:
> Should the code that promotes this value also mask the low 3 bits, thus `and`ing this value with `splat(7)` ?
We could do, but whenever the type is promoted to something that has to be stored out to memory there will have to be a zero- or sign-extend. At that point the `and` will definitely appear. I wasn't sure if this is something that we need to do explicitly as part of lowering stepvector because I just assumed that the remaining bits would be treated as undefined.

Having said that, if you still think it's worthwhile adding an explicit mask I can look into it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113655/new/

https://reviews.llvm.org/D113655